Project flow for ASIC and FPGA Designs PDF Print E-mail

 

Firstly, our application engineers will find out what your specific needs are. Thereafter they will develop an understanding of the design challenges. At this initial step the customers' verbal description and outline of the design will suffice.

 

In phase 2 the specification of the projected design will outline the sope of performance concerning the application need, the design times and the schedule. After the customers' approval the design start-up procedure as well as the implementation plan will be initiated. Modifications will be transparently discussed with the customer, captured and only implemented with the approval of the customer. Finally the results are documented and the application certified.

 

Smartlogic provides the easiest path for designs that meet your requirements.

 

 
PCI-Express Basics

Obtain a short overview about
PCI-Express from our
PPT presentation.
Download PCI-Express basics

 
Meet us at:

XILINX X-Fest

May 10th. 2012 in Munich

FPGA Days 2012

June 19th - 21st. in Stuttgart

 


 
IP-Cores

Smartlogic offers its own proven IP cores. Available are free cores as well as highly specialized silicon proven cores, which are subject to a charge. Smartlogic's own cores are free from the rights of third parties.

Read more on this under "IP".

 
Innovation Benefits Baden-Wuerttemberg

Is your headoffice situated in Baden-Wuerttemberg?

Then you might be qualified for innovation benefits placing your design order with us.

Read more on this topic.