Simply faster with our FPGA IP Cores

With our proven IP Cores you can connect the PCI Express or the Ethernet world with your FPGA application within a few hours. To give you a quick impression whether our products are suitable for you, we have compiled typical use cases for you right at the beginning. On the corresponding application page we show you details and give you a recommendation which IP product is the right one for you. Have a look at our application video.

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In just 4 minutes you will get an introduction and a short overview of our IP products as well as selected use cases. This makes it very easy for you to get an impression if these are suitable for your application. Our application overview, which we are constantly expanding, shows you further examples.


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The AXI Bridge with DMA IP core is Smartlogic’s ultimate PCIe DMA IP solution with a powerful mix of multiple industry standard AXI Interfaces. AXI Stream interfaces allow continuous data streaming from FPGA to Host or from Host to FPGA. S-AXI Memory mapped interfaces allow easy data access of remote memories in order to realize shared memory access or peer-to-peer applications.

Quality that convinces

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The HCC PCIe DMA IP Core from Smartlogic has greatly reduced our FPGA design effort and decreased our time to market.
Smartlogic’s expert support team is responsive and knowledgeable—they’ve helped us quickly integrate their IP into our design.

Wayne Swope, AMERGINT Technologies, Inc., an ARKA Group company, Colorado Springs USA
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We were in the market for a turnkey, robust PCIe DMA solution and Smartlogic’s HCC PCIe DMA core more than delivered. Smartlogic’s solution provided us with a high-speed and dependable PCIe infrastructure that met the demanding requirements of our real-time digital signal processing technologies.

Brent Hrabski, Tevet LLC, Greeneville, Tennessee, USA

Whitepaper and Application Notes

Arria 10 Demo Design and Bitstream

This application note explains the features of the Arria 10 demo design for the DreamChip evaluation board

Completion Sorting

This whitepaper describes the protocol rules regarding completions returning on read requests and what needs to be considered

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Meet us in Munich at the FPGA conference 2024

Get in touch for more information

+49 7031 43 90
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