Products
Our IP products include extensive protocol know-how and powerful DMA engines and are used in many projects of our customers worldwide. For many companies the decision to use an IP core from Smartlogic, is based on the consideration to license a proven IP core at a fraction of the cost compared to an in-house development. At the same time, the company\'s own development capacity can logically be used to bring the end product to market more quickly.
Due to the uncompromising use of state-of-the-art coding techniques such as RAM inferring, our IP cores are suitable for all device families from AMD, Altera and other FPGA manufacturers.
Modern licensing models allow you to license the products in the way you need. Even source code licensing without any limitations, e.g. necessary for open source scans, is possible with us.
More details about each of our products can be found on our product pages.
High-Channel-Count DMA IP Core
The High Channel Count DMA IP was tailored for high end PCI Express DMA applications and has a significantly larger functional range than the flex IP core. It can be used to solve very demanding solutions with up to 64 independent upstream and 16 downstream data channels.
Multi-Channel AXI DMA Engine
The Multi-Channel AXI DMA Engine combines a powerful AXI DMA engine with a protocol conversion of up to 16 AXI stream channels to AXI and vice versa. The included Linux driver allows Zynq or SoC software applications to access and process the data easily and quickly.
AXI Bridge for PCIe IP Core
The AXI Bridge for PCIe IP core is Smartlogic’s IP solution with up to 4 separate memory mapped AXI4 Interfaces. The AXI Bridge IP core translates the AXI4 memory read or writes to PCI-Express Transaction Layer Packets and translates PCIe memory read and write requests to AXI4 transactions.
AXI Bridge with DMA for PCIe IP Core
The AXI Bridge with DMA IP core is Smartlogic’s ultimate PCIe DMA IP solution with a powerful mix of multiple industry standard AXI Interfaces. AXI Stream interfaces allow continuous data streaming from FPGA to Host or from Host to FPGA. S-AXI Memory mapped interfaces allow easy data access of remote memories in order to realize shared memory access or peer-to-peer applications.