AXI Bridge for PCIe IP Core

The AXI Bridge for PCIe IP core is Smartlogic’s IP solution with up to 4 AXI4 memory mapped interfaces. The AXI Bridge IP core translates the AXI4 memory read or writes to PCI-Express Transaction Layer Packets and translates PCIe memory read and write requests to AXI4 transactions.

All interfaces support fully parallel operation without any interferences. Interfaces that are not required can be turned off individually and do not occupy logic resources.

This IP core enables the developer to build complex PCI-Express endpoints with no specific PCI Express protocol know-how. The user only transmits or receives payload data and does not have to assemble valid PCI-Express TLP packets.

A powerful kernel mode device driver is shipped with the IP for Windows and Linux OS to ensure easy software integration of the core.